1. Field of the Invention
This invention relates to a pulse width modulation circuit which performs modulation of pulse widths based on input data. This invention also relates to a multiphase clock generation circuit which can be used in this pulse width modulation circuit.
2. Description of Related Art
In recent years, laser beam printers (LBPs) and digital copy equipment equipped with lasers have been widely adopted, due to their high resolution and their quiet and fast operation. The pulse width modulation (PWM) method is primarily used for control of printing grayscales in such equipment. Pulse width modulation method is a method in which the grayscale (that is, the density) of each printed dot is controlled through a pulse width.
Conventional pulse width modulation circuitry can be broadly divided into two types, which are counter types and delay types. A counter-type circuit is for example disclosed in Japanese Unexamined Patent Application Publication No. 56-69929. In this counter-type circuit, a reference clock is counted by a counter circuit, and the count value and a digital pulse data value, that is, input data, are compared by a comparator; when the result of comparison indicates coincidence, the pulse width modulation output, that is, the PWM output, is changed.
The delay method is for example disclosed in Japanese Unexamined Patent Application Publication No. 6-177723. In this delay method, a reference clock is input to a delay circuit, and from the plurality of delay signals output from the delay circuit, that signal corresponding to a digital pulse data value is selected, and the PWM output is changed.
However, there is the problem that in the cases of the counter method and delay method used in conventional pulse width modulation circuits, it is difficult to achieve fast and precise operation, and these methods are not suitable for lowering costs.
For example, consider a case in which PWM pulses are to be generated at 100 MHz with 8-bit resolution. In this case, time-conversion of the resolution yields 1 s/100 MHz/28=40 ps. In the counter method, this means that a counter circuit is necessary which operates with a clock period tCK=40 ps or less. In the delay method, this means that the delay time per cell stage in the delay circuit must be 40 ps or less. It is difficult to realize such performance using current CMOS technology.
On the other hand, by performing interleaving processing, the 40 ps constraint can be relaxed; but in this case the number of interleave divisions is large (16 to 32), so that such new problems as increased circuit scale and scattering among the phases of each stage arise.
Hence in order to resolve the above problems, in Japanese Patent Application No. 2004-196354, which is correspond to U.S. Patent Publication No. US-2006-0001467-A1, the applicant proposed a pulse width modulation circuit which utilizes multiphase clock signals. This pulse width modulation circuit is explained briefly below.
FIG. 14 is a block diagram showing an entire pulse width modulation circuit of the previous application. This pulse width modulation circuit comprises a multiphase clock generation circuit 2, synchronization position detection circuit 3, digital pulse data signal processing circuit 4, multiphase clock (CLK) selection circuit 5, and pulse width modulation signal generation circuit 6.
A reference clock signal is input to the multiphase clock generation circuit 2 from the input terminal 1. This multiphase clock generation circuit 2 generates multiphase clock signals based on the input reference clock, and outputs the signals to a synchronization position detection circuit 3 and multiphase clock selection circuit 5. The multiphase clock generation circuit 2 generates multiphase clock signals by phase interpolation of intermediate clock signals generated by a phase-locked loop circuit. The multiphase clock signals include clock signals with 256 (=28) phases in the case of 8-bit resolution.
The multiphase clock signals output from the multiphase clock generation circuit 2 and a horizontal sync signal which is a reference signal are input to the synchronization position detection circuit 3. The synchronization position detection circuit 3 detects the clock signal among the multiphase clock signals with which the horizontal sync signal is synchronized. A synchronization position detection signal indicating the result of synchronization position detection is output to the digital pulse data signal processing circuit 4 and to the multiphase clock selection circuit 5.
The digital pulse data which is the input data, and the synchronization position detection signal output from the synchronization position detection circuit 3, are input to the digital pulse data signal processing circuit 4. The digital pulse data signal processing circuit 4 converts the input digital pulse data into PWM pulse rising-edge and falling-edge information according to the synchronization position detection result, in order to synchronize the PWM pulses with the horizontal sync signal. Signals containing rising-edge and falling-edge information are output to the multiphase clock selection circuit 5.
The multiphase clock signals output from the multiphase clock generation circuit 2, the synchronization position detection signals output from the synchronization position detection circuit 3, and the signals containing rising-edge and falling-edge information output from the digital pulse data signal processing circuit 4, are input to the multiphase clock selection circuit 5. The multiphase clock selection circuit 5 selects arbitrary clock signals from among the multiphase clock signals, according to the rising-edge and falling-edge information. The selected clock, that is, the selection clock signal, is output to the pulse width modulation signal generation circuit 6.
The selection clock signal is input by the multiphase clock selection circuit 5 to the pulse width modulation signal generation circuit 6. The pulse width modulation signal generation circuit 6 generates pulse width modulation signals (PWM pulses) based on selection clock signals. These pulse width modulation signals are for example signals used to modulate laser output.
FIG. 15 shows an example of the specific circuit configuration of a multiphase clock generation circuit 2. In the multiphase clock generation circuit 2, a combination of a phase-locked loop (PLL) circuit and a phase interpolation circuit is used as the circuit which generates multiphase clock signals. In the previous application, when the oscillator of a PLL circuit alone is used to generate clock signals with 256 phases, it is difficult to achieve fast operation; and when a phase interpolation circuit alone is used to generate clock signals with 256 phases, there is an increase in error, and precision is degraded due to scattering in manufacturing processes. Hence a configuration was adopted in which both are used.
As shown in FIG. 15, the multiphase clock generation circuit 2 comprises a phase comparator 201, charge pump circuit 202, filter 203, VCO (Voltage Controlled Oscillator) circuit 204, phase interpolation circuit 205, output buffer 206, and delay circuit 207.
The phase comparator 201 receives as input the reference clock, performs processing for phase comparison of the rising waveform of the reference clock with the rising waveform of a feedback clock input via the delay circuit 207, and generates pulse information for the phase difference. The charge pump circuit 202 converts the phase different pulse information generated by the phase comparator 201 into current information.
The signal output from the charge pump circuit 202 is filtered by the filter 203 and output to the VCO circuit 204. The oscillation frequency of the VCO circuit 204 changes according to the input signal, to generate an intermediate clock signal. In this example, intermediate clock signals with 32 phases are generated. The VCO circuit 204 consists of a ring oscillator, in which 32 stages of differential amplifiers are connected in series, and the output of the final stage is inverted and input to the first stage. The outputs of each of the 32 stages of series-connected differential amplifiers become the intermediate clock signals with 32 phases. As the VCO circuit 204, the ring oscillator of Japanese Patent No. 3512676 can also be used.
The intermediate clock signals generated in the VCO circuit 204 are input to the phase interpolation circuit 205. The phase interpolation circuit 205 further increases the phases of the intermediate clock signals, to generate multiphase clock signals. In this example, the number of phases is increased in order from 32-phase intermediate clock signals to 64-phase clock signals, from 64-phase clock signals to 128-phase clock signals, and from 128-phase clock signals to 256-phase clock signals CLKIP[0] to CLKIP[255]. As the phase interpolation circuit 205, the timing difference division circuit described in Japanese Unexamined Patent Application Publication No. 2001-339280 can also be used.
Multiphase clock signals with the number of phases increased to 256 are output via the output buffer 206. Of these multiphase clock signals, the CLKIP[0] signal is fed back, is delayed a prescribed amount by the delay circuit 207, and is then input to the phase comparator 201.
By means of the above-described pulse width modulation circuit of the previous application, pulse width modulation can be performed rapidly and with high precision, and printing grayscales and other factors can be controlled appropriately when applied to laser beam printers. However, when used in laser beam printers employing a plurality of drums or in other cases, there may be causes in which fine adjustment of pulse frequencies is necessary in order to correct for scattering between drums.
In such a case, it is conceivable that by providing a variable frequency divider between the reference clock and the phase comparator 201, and between the delay circuit 207 and the phase comparator 201 in the previous application, and by controlling the division ratio, the frequencies of the multiphase clock signals output from the output buffer 206 can be adjusted.
However, if an attempt is made to fine-adjust the frequency using a frequency divider circuit, the switching unit is one cycle, and so it is anticipated that jitter may occur during phase comparison. For example, even if the switching unit is kept small in combination with the multiphase output, in order to fine-adjust the frequency an extremely high division ratio would be necessary, leading to a decline in the jitter cutoff characteristic due to the lowered phase comparison frequencies and worsening of PLL responsiveness due to the lowered loop band. Hence the characteristics are inappropriate as the reference frequency of high-precision PWM output.
For these reasons, there has been a need for a function for frequency fine-tuning in pulse-width modulation circuits and multiphase clock generation circuits from which high precision is demanded.